The present invention relates to memory devices and methods of fabricating the same, more specifically, to ferroelectric memory devices and methods of fabricating the same.
When an external voltage is applied to electric dipoles arranged in a ferroelectric material, the electric dipoles may be selectively polarized. Application of a reverse external field causes polarization in an opposite direction. The ferroelectric material generally has a hysteresis depending on a magnitude and direction of the applied electric field from the external voltage. An integrated circuit memory device writing and reading information using this property of a ferroelectric material is referred to ferroelectric memory device. A ferroelectric memory device may be used as a non-volatile memory device in which stored data can be retained even when power to the memory device is turn off. Such a ferroelectric memory device is further described, for example, in literature cited “Integration of Ferroelectric Capacitor Technology with CMOS” (Moazzami et al.), 1994 Symposium on VLSI Technology Digest of Technical Papers (Tatsumi Sumi et al.), pp. 55–56 and 1994 IEEE International Solid-State Circuits Conference, pp. 268.
A capacitor of a ferroelectric memory device may use noble metals (e.g., iridium, platinum and oxides thereof) as an upper and lower electrode. The capacitor may have a planar structure and a ferroelectric material thin film may be formed, for example, by sol-gel, sputtering and/or CVD methods or the like, on a planar lower electrode. As with other known types of integrated circuit (semiconductor) memory devices, as integration increases, cell dimensions of the ferroelectric memory device may become short and the corresponding dimensions of a cell capacitor also becomes shorter. In such highly integrated devices, a three dimensional capacitor (e.g., cylindrical-type or column type) may be formed to obtain a desired capacitance within the allotted space.
An example of a column-type capacitor structure is discussed in U.S. Pat. No. 6,268,260 assigned to Lam Research Incorporation. An example of a cylindrical-type capacitor structure is discussed in U.S. Pat. No. 6,238,963 assigned to IBM Incorporation. The described capacitors are proposed to address issues related to the disadvantages of a conventional plane capacitor due to limitations on the capacitor's assigned dimensions and to address a thin film of ferroelectric layer and limitations on the upper and lower electrodes.
FIG. 1 is cross-sectional illustration of a prior art ferroelectric memory device having a column-type capacitor. As shown in FIG. 1, the ferroelectric memory device includes a transistor(s) 3 a bit line 13 and column-type capacitor(s) 25. The transistor, including a gate electrode, is formed on an integrated circuit (semiconductor) substrate 1 between isolation layers 2. The bit line 13 is electrically connected to a source region 5a of the transistor 3 and is formed on a first interlayer dielectric (ILD) 9. A column-type capacitor 25 is electrically connected to each drain 5b of the transistor 3 and is formed on a second interlayer dielectric 15.
Each capacitor 25 includes a lower electrode 19, which may be of noble metal group, a ferroelectric layer 21 and an upper electrode 23. The ferroelectric layer 21 is interposed between the lower electrode 19 and the upper electrode 23. The bit line 13 may be electrically connected to the source 5a via a direct contact 11 interposed therebetween and the lower electrode 19 of each capacitor 25 may be electrically connected to a drain 5b via a buried contact 17 interposed therebetween. Alternatively, a direct contact 11 may be electrically connected to the source 5a via a first contact pad 7a interposed therebetween, and the buried contact 17 may be electrically connected to the drain 5b via a second contact pad 7b interposed therebetween.
Fabricating the capacitor 25 may include the steps of depositing and patterning noble materials to form the lower electrode 19 and depositing the ferroelectric on the lower electrode 19 and the second interlayer dielectric 15 to form the ferroelectric layer 21. Advantages of such a method may include reduction or prevention of degradation of the ferroelectric characteristic as the ferroelectric material may not be etched in forming the ferroelectric layer 21. In addition, the capacitance may be increased by increasing the size of the lower electrode 19. Disadvantages may arise in fabricating the ferroelectric memory device of FIG. 1. Two steps are generally required to form the lower electrode 19 of the capacitor 25. First, noble-metal group materials are relatively thickly deposited. Subsequently, an etching process is used for patterning the noble-metal group materials to form the lower electrode. As a result, the manufacturing costs may be increased because of the relatively thick deposition of the noble-metal group materials. Furthermore, it may be difficult for thickly deposited noble-metal group materials to be patterned to fabricate the lower electrode.
FIG. 2 is cross-sectional view illustrating a prior art ferroelectric memory device equipped with a cylindrical-type capacitor. As shown in FIG. 2, such a ferroelectric memory device includes a capacitor 25′ equipped with a cylindrical structure that is formed on a third interlayer dielectric 18′. The structure in FIG. 2 is otherwise substantially the same as that illustrated in FIG. 1 and such common aspects will not be further described with reference to FIG. 2. For the cylindrical capacitor 25′, surface dimensions of the electrodes may be further extended, which may further increase the capacitance.
As shown in FIG. 2, holes 20′ may be formed by removing a part of the third interlayer dielectric 18′ before forming the lower electrode 19′ of a cylindrical capacitor. If the aspect ratio of the holes 20′ rises, it may be difficult for the cylindrical capacitor 25′ to be formed depending on a step coverage characteristic of the lower electrode 19′. To form a cylindrical capacitor 25′ in narrow holes 20′, there may be a need to form a thin film of the lower electrode 19′, the ferroelectric 21′ and the upper electrode 23′ in respective process steps. In addition, the upper electrode 23 (or 23′) may be misaligned with respect to the lower electrode 19 (or 19′).